In a semiconductor apparatus including a semiconductor made of, for example, silicon carbide, a forward current caused to flow through a PN diode prompts nucleation associated with recombination of electrons and positive holes, resulting in the growth of stacking faults expanding from basal plane dislocations in a semiconductor substrate. Unfortunately, this causes the relevant region to be highly resistive.
As a method of testing for the presence or absence of the stacking faults generated as described above, the occurrence of forward voltage degradation (voltage increase) is detected after one-hour energization at a current density of 100 [A/cm2] in a forward direction of the PN diode (see Patent Document 1).
It has been shown that the forward voltage degradation would occur if a product provided with measures against forward voltage degradation is energized at a current density of 200 [A/cm2] or more or if the product is energized at a current density of 100 [A/cm2] at a high temperature over 200° C. (see Patent Document 2).
As another example, it has been reported that the forward voltage degradation occurred due to 4.5 hour energization at a current density of 600 [A/cm2] and thus no light emission associated with electroluminescence (EL) was observed in some places due to defects (see Non-Patent Document 1).